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Message from the Chairs

Reducing Parallelizing Compilation Time by Removing Redundant Analysis
Jixin Han, Rina Fujino, Ryota Tamura, Mamoru Shimaoka, Hiroki Mikami, Moriyuki Takamura, Sachio Kamiya, Kazuhiko Suzuki, Takahiro Miyajima, Keiji Kimura, and Hironori Kasahara
(Waseda University, Japan; OSCAR TECHNOLOGY, Japan)


@InProceedings{SEPS16p1, author = {Jixin Han and Rina Fujino and Ryota Tamura and Mamoru Shimaoka and Hiroki Mikami and Moriyuki Takamura and Sachio Kamiya and Kazuhiko Suzuki and Takahiro Miyajima and Keiji Kimura and Hironori Kasahara}, title = {Reducing Parallelizing Compilation Time by Removing Redundant Analysis}, booktitle = {Proc.\ SEPS}, publisher = {ACM}, pages = {1-0}, doi = {}, year = {2016}, }

A Divide-and-Conquer Parallel Pattern Implementation for Multicores
Marco Danelutto, Tiziano De Matteis, Gabriele Mencagli, and Massimo Torquati
(University of Pisa, Italy)


@InProceedings{SEPS16p11, author = {Marco Danelutto and Tiziano De Matteis and Gabriele Mencagli and Massimo Torquati}, title = {A Divide-and-Conquer Parallel Pattern Implementation for Multicores}, booktitle = {Proc.\ SEPS}, publisher = {ACM}, pages = {11-10}, doi = {}, year = {2016}, }

Parallel Evaluation of a DSP Algorithm using Julia
Peter Kourzanov
(NXP, Netherlands; Delft University of Technology, Netherlands)


@InProceedings{SEPS16p21, author = {Peter Kourzanov}, title = {Parallel Evaluation of a DSP Algorithm using Julia}, booktitle = {Proc.\ SEPS}, publisher = {ACM}, pages = {21-20}, doi = {}, year = {2016}, }

Exhaustive Analysis of Thread-Level Speculation
Clark Verbrugge, Christopher J. F. Pickett, Alexander Krolik, and Allan Kielstra
(McGill University, Canada; IBM, Canada)


@InProceedings{SEPS16p31, author = {Clark Verbrugge and Christopher J. F. Pickett and Alexander Krolik and Allan Kielstra}, title = {Exhaustive Analysis of Thread-Level Speculation}, booktitle = {Proc.\ SEPS}, publisher = {ACM}, pages = {31-30}, doi = {}, year = {2016}, }