LCTES 2026 – Proceedings

27th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2026)

Frontmatter

Advanced Compiler Tuning

RAPO: Retrieval-Augmented Phase Ordering
Jinwook Yang, Junghyun Lee, Yeonsun ­Hong, and Hyojin Sung
(Seoul National University, Republic of Korea)

Publisher's Version Article: pldiws26lctesmain-p50-p (type: Full Paper) doi:10.1145/3814943.3816172

CausalTuner: Feature-Aware Causal Guidance for Compiler Auto-tuning
Jiaqing Zhong, Juan Chen, Yichang Zhou, and Kuan Li
(National University of Defense Technology, China; Dongguan University of Technology, China)

Publisher's Version Published Artifact Artifacts Available Artifacts Reusable Results Reproduced Article: pldiws26lctesmain-p93-p (type: Full Paper) doi:10.1145/3814943.3816181

Reproduction Package for Article 'CausalTuner: Feature-Aware Causal Guidance for Compiler Auto-tuning' (doi:10.5281/zenodo.20578672): CausalTuner is a research prototype for compiler auto-tuning that integrates precomputed causal inference rules into a genetic algorithm to optimize program performance. Notably, the open-source code only implements the llama.cpp tuning environment and the core causalga optimizer.

Empirical Observations about Profile-Guided Optimizations for Mainstream C/C++ Compilers
Soma Pal and Prasad Anil Kulkarni
(University of Kansas, USA)

Publisher's Version Article: pldiws26lctesmain-p88-p (type: Full Paper) doi:10.1145/3814943.3816180

Binary Optimization and System Security

DeduBB: Binary Code Size Reduction via Post-Link Basic Block Deduplication
Chaitanya Mamatha Ananda, Mahbod Afarin, Rajiv Gupta, Sriraman Tallam, Han Shen, and Xinliang David Li
(University of California at Riverside, USA; Google, USA)

Publisher's Version Published Artifact Artifacts Available Artifacts Reusable Results Reproduced Article: pldiws26lctesmain-p31-p (type: Full Paper) doi:10.1145/3814943.3816169

DeduBB: Binary Code Size Reduction via Post-Link Basic Block Deduplication (doi:10.5281/zenodo.20261031): This artifact contains the pre-built optimizer binaries, baseline profiles, and automated evaluation workloads for DeduBB. It includes pre-configured, containerized Docker environments for both Arm (AArch64) and x86 architectures to evaluate post-link basic block deduplication capabilities.

SymFlow: Event-Chain-Aware Symbolic Execution for Serverless Sensitive Data Flow Detection
Yuanpeng Wang, Zhineng Zhong, Zhenkai Liang, Ding Li, Yao Guo, and Xiangqun Chen
(Peking University, China; National University of Singapore, Singapore)

Publisher's Version Article: pldiws26lctesmain-p21-p (type: Full Paper) doi:10.1145/3814943.3816168

CVS: A Metric for Security-Aware Compilation against Side-Channel Attacks in Edge SoCs (WIP)
Yi Han, Puhong Lei, Yang Shi, Zhe Li, Xing Mou, Jianjun Chen, and Yaohua Wang
(National University of Defense Technology, Changsha, China; Key Laboratory of Advanced Microprocessor Chips and Systems, Changsha, China; Hunan Greatwall Galaxy Science and Technology, Changsha, China)

Publisher's Version Article: pldiws26lctesmain-p71-p (type: Short Paper (4 pages + references)) doi:10.1145/3814943.3816178

A Programming Model for Efficient Inter-Kernel Control-Flow on Memory-Mapped Near-Data Processing Architecture (WIP)
Seungheon Lee, Wonhyuk Yang, Seonyeong Heo, and Gwangsun Kim
(POSTECH, Republic of Korea; Kyung Hee University, Republic of Korea)

Publisher's Version Article: pldiws26lctesmain-p112-p (type: Short Paper (4 pages + references)) doi:10.1145/3814943.3816184

FLUX: Frequency Scaling with Layer-wise Utilization for Energy-Efficient NPU Execution (WIP)
Inho Lee, Ky Yeop Lim, Hyejun Kim, Beomseok Kim, Dongsuk Jeon, Hunjun Lee, and Yongjun Park
(Hanyang University, Republic of Korea; Samsung Electronics, Republic of Korea; Yonsei University, Republic of Korea; Seoul National University, Republic of Korea)

Publisher's Version Article: pldiws26lctesmain-p69-p (type: Short Paper (4 pages + references)) doi:10.1145/3814943.3816177

Formal Methods and Systems Reliability

Towards Verifiable System Code using a DSL Compiled to Efficient and Readable C Code
Clément Chavanon, Henrik Karlsson, Frédéric Besson, Sandrine Blazy, and Roberto Guanciale
(Inria - Univ Rennes - CNRS - IRISA, France; KTH Royal Institute of Technology, Sweden; Univ Rennes - Inria - CNRS - IRISA, France)

Publisher's Version Published Artifact Artifacts Available Artifacts Reusable Results Reproduced Article: pldiws26lctesmain-p40-p (type: Full Paper) doi:10.1145/3814943.3816170

Artifact for "Towards Verifiable System Code using a DSL Compiled to Efficient and Readable C Code", at LCTES'26 (doi:10.5281/zenodo.20086279): This artifact archives the source code of the Barocq compiler and of the Barocq port of the S3K microkernel. It takes the form of a Docker container that has the Barocq binary pre-installed, for compiling the paper example and S3K, and it also comes with the Rocq Prover to evaluate the Rocq files generated from those ...

A Pointer-Ownership Model for C Inspired by Rust
David Svoboda, William Klieber, Lori Flynn, Ruben Martins, and Jeffrey Hoskinson
(Carnegie Mellon University, USA)

Publisher's Version Published Artifact Artifacts Available Artifacts Reusable Results Reproduced Article: pldiws26lctesmain-p95-p (type: Full Paper) doi:10.1145/3814943.3816182

Reproduction Artifact for a Pointer-Ownership Model for C Inspired by Rust (doi:10.5281/zenodo.20158172): This artifact accompanies the accepted LCTES 2026 paper "A Pointer-Ownership Model for C Inspired by Rust”. The Pointer Ownership Model (POM) consists of a temporal memory-safety model for C code, a p-model generator that specifies (in a YAML file) the application of POM to a particular program, and an automated ...

Hikami: A Lightweight Hypervisor for Emulating RISC-V Extension Semantics with Sail-Driven Auto-generation
Norimasa Takana and Yoshihiro Oyama
(University of Tsukuba, Japan)

Publisher's Version Published Artifact Artifacts Available Artifacts Reusable Results Reproduced Article: pldiws26lctesmain-p45-p (type: Full Paper) doi:10.1145/3814943.3816171

Reproduction Package for `Hikami: A Lightweight Hypervisor for Emulating RISC-V Extension Semantics with Sail-Driven Auto-Generation' (doi:10.5281/zenodo.20226662): This artifact provides the complete source code, evaluation framework, and pre-built binaries supporting the LCTES 2026 paper #45. It includes "Hikami", a lightweight RISC-V hypervisor, and "Ozora", a framework for automatically generating instruction emulation logic directly from formal Sail specifications. The ...

Scheduled Partial-Credit RL for Reliable Code Generation with Small Language Models (WIP)
Suryansh Singh Sijwali and Suman Saha
(Pennsylvania State University, USA)

Publisher's Version Article: pldiws26lctesmain-p11-p (type: Short Paper (4 pages + references)) doi:10.1145/3814943.3816167

Specialized Hardware and Accelerator Design

Can Fine-Grain Multi-threading Subsume VLIW?
Scott Pomerville, Soner Önder, Gang-Ryung Uh, and David Whalley
(Northern Michigan University, USA; Michigan Technological University, USA; Florida State University, USA)

Publisher's Version Article: pldiws26lctesmain-p73-p (type: Full Paper) doi:10.1145/3814943.3816179

Sirop: A Small IR for HLS with Parallel Patterns
Louis Hildebrand and Christophe Dubach
(McGill University, Canada; MILA, Canada)

Publisher's Version Published Artifact Artifacts Available Artifacts Reusable Results Reproduced Article: pldiws26lctesmain-p61-p (type: Full Paper) doi:10.1145/3814943.3816175

Sirop: A Small IR for HLS with Parallel Patterns (LCTES '26 Artifact) (doi:10.5281/zenodo.20090976): This is the artifact for the paper "Sirop: A Small IR for HLS with Parallel Patterns," for the LCTES '26 artifact evaluation. paper61.zip is the main artifact. It includes the source code for Sirop, a Docker image that contains the pre-built Sirop compiler, and some scripts to help with evaluation. ...

A Functional Approach to Synthesizing Routable Programmable Accelerators for Neural Networks
Tzung-Han Juang, Paul Teng, and Christophe Dubach
(McGill University, Canada; MILA, Canada)

Publisher's Version Published Artifact Artifacts Available Artifacts Reusable Results Reproduced Article: pldiws26lctesmain-p99-p (type: Full Paper) doi:10.1145/3814943.3816183

(Artifact) A Functional Approach to Synthesizing Routable Programmable Accelerators for Neural Networks (doi:10.5281/zenodo.20046007): This artifact contains logic to evaluate a LCTES '26 paper titled A Functional Approach to Synthesizing Routable Programmable Accelerators for Neural Networks. The paper presents a functional programming–based approach for expressing synthesizable, runtime-programmable hardware accelerators. It supports dynamic shapes ...

LoopHint: A Compiler-Assisted Loop Branch Predictor for Embedded DSPs
Yuanyang Xiang, Chen Xu, Ruozhou Xiao, and Zhiwei Zhang
(Institute of Automation at Chinese Academy of Sciences, China; University of Chinese Academy of Sciences, China)

Publisher's Version Article: pldiws26lctesmain-p1-p (type: Full Paper) doi:10.1145/3814943.3816166

Memory Efficiency and Control-Flow Analysis

MemSpec: Memory-Aware Runtime for Adaptive Draft Scheduling in Speculative Decoding on Edge Devices
Eunjeong Kim, Yeong Jun Jeon, and Myeonggyun Han
(Kyungpook National University, Republic of Korea)

Publisher's Version Article: pldiws26lctesmain-p56-p (type: Full Paper) doi:10.1145/3814943.3816174

Bridging the Memory Hotness Gap in Edge Systems with Hotness-Segregated Object Allocation
Ruizhe Huang, Jiahua Wang, Qihang Xu, Peng Jiang, Zhida An, Ding Li, Yao Guo, Xiangqun Chen, Yuxin Ren, and Ning Jia
(Peking University, China; Southeast University, China; Huawei Technologies, China)

Publisher's Version Article: pldiws26lctesmain-p64-p (type: Full Paper) doi:10.1145/3814943.3816176

On the Origins of Indirect Jumps in Embedded Software
Ariane Nicolas, Ronan Lashermes, Isabelle Puaut, and Erven Rohou
(Univ Rennes - Inria - CNRS - IRISA, France; Rambus, Netherlands)

Publisher's Version Published Artifact Artifacts Available Artifacts Reusable Results Reproduced Article: pldiws26lctesmain-p55-p (type: Full Paper) doi:10.1145/3814943.3816173

Artifact for the paper "On the Origins of Indirect Jumps in Embedded Software" (doi:10.1145/3747416): This artifact accompanies the paper "On the Origins of Indirect Jumps in Embedded Software". It provides a static analysis tool for RISC-V binaries that identifies and classifies generated indirect jumps (jalr) and reports the proportion of jumps belonging to each category. The artifact is distributed as a Docker ...

proc time: 0.05