LCTES 2025 – Proceedings

Results Reproduced Article: pldiws25lctesmain-p23-p (type: Full Paper) doi:10.1145/3735452.3735523

	SPARQ: An Accelerator Architecture for Large Language Models with Joint Sparsity and Quantization Techniques (Video): Video of conference presentation
	SPARQ: An Accelerator Architecture for Large Language Models with Joint Sparsity and Quantization Techniques (doi:10.5281/zenodo.15385238): This repository contains the hardware design files and synthesis scripts for SPARQ-MXU-SI, an energy-efficient matrix execution unit optimized for sparse matrix operations. The architecture and evaluation results are described in our LCTES 2025 paper.

ADaPS: Adaptive Data Partitioning to Parallelize CNN Inference on Resource-Constrained Hardware
Jaume Mateu Cuadrat and Bernhard Egger
(Seoul National University, Republic of Korea)

Publisher's Version Article: pldiws25lctesmain-p81-p (type: Full Paper) doi:10.1145/3735452.3735532

ADaPS: Adaptive Data Partitioning to Parallelize CNN Inference on Resource-Constrained Hardware (Video): Video of conference presentation

Graphitron: A Domain Specific Language for FPGA-Based Graph Processing Accelerator Generation
Xinmiao Zhang, Zheng Feng, Shengwen Liang, Xinyu Chen, Lei Zhang, and Cheng Liu
(Institute of Computing Technology at Chinese Academy of Sciences, China; University of Chinese Academy of Sciences, China; Hong Kong University of Science and Technology, Guangzhou, China)

Publisher's Version Article: pldiws25lctesmain-p89-p (type: Full Paper) doi:10.1145/3735452.3735533

Graphitron: A Domain Specific Language for FPGA-Based Graph Processing Accelerator Generation (Video): Video of conference presentation

Modeling and Verification of Sigma Delta Neural Networks using Satisfiability Modulo Theory
Sirshendu Das, Ansuman Banerjee, and Swarup Kumar Mohalik
(Indian Statistical Institute, Kolkata, India; Ericsson Research, India)

Publisher's Version Article: pldiws25lctesmain-p28-p (type: Full Paper) doi:10.1145/3735452.3735525

Modeling and Verification of Sigma Delta Neural Networks using Satisfiability Modulo Theory (Video): Video of conference presentation

Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP)
Siyi Xu, Limin Jiang, Yintao Liu, Yihao Shen, Yi Shi, Shan Cao, and Zhiyuan Jiang
(Shanghai University, China)

Artifacts Reusable Article: pldiws25lctesmain-p58-p (type: Full Paper (5 pages + references)) doi:10.1145/3735452.3735526

(Artifact) Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP) (doi:10.5281/zenodo.15291421): We have deployed the toolchain mentioned in the paper "Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP)" into a Docker environment. Please refer to the source code on https://github.com/ACELab-SHU/LCTES-25-Artifact.

Towards Macro-Aware C-to-Rust Transpilation (WIP)
Robbe De Greef, Attilio Discepoli, Esteban Aguililla Klein, Théo Engels, Ken Hasselmann, and Antonio Paolillo
(Vrije Universiteit Brussel, Belgium; Université Libre de Bruxelles, Belgium; Royal Military Academy of Belgium, Belgium)

Publisher's Version Article: pldiws25lctesmain-p106-p (type: Full Paper (5 pages + references)) doi:10.1145/3735452.3735535

Towards Macro-Aware C-to-Rust Transpilation (WIP) (Video): Video of conference presentation

Embedded Systems and Real-Time Optimization

rtesbench: A Multi-core Benchmark Framework for Real-Time Embedded Systems
Yixiao Xing, Yixiao Li, and Hiroaki Takada
(Nagoya University, Japan)

Info Article: pldiws25lctesmain-p3-p (type: Full Paper) doi:10.1145/3735452.3735521

rtesbench: A Multi-core Benchmark Framework for Real-Time Embedded Systems (Video): Video of conference presentation

ASC-Hook: Efficient System Call Interception for ARM
Yang Shen, Min Xie, Tao Wu, Wenzhe Zhang, Ruibo Wang, and Gen Zhang
(National University of Defense Technology, China; Changsha University of Science and Technology, China)

Publisher's Version Article: pldiws25lctesmain-p24-p (type: Full Paper) doi:10.1145/3735452.3735524

ASC-Hook: Efficient System Call Interception for ARM (Video): Video of conference presentation

SSFFT: Energy-Efficient Selective Scaling for Fast Fourier Transform in Embedded GPUs
Dongwon Yang, Jaebeom Jeon, Minseong Gil, Junsu Kim, Seondeok Kim, Gunjae Koo, Myung Kuk Yoon, and Yunho Oh
(Korea University, Republic of Korea; Ewha Womans University, Republic of Korea)

Publisher's Version Article: pldiws25lctesmain-p66-p (type: Full Paper) doi:10.1145/3735452.3735529

SSFFT: Energy-Efficient Selective Scaling for Fast Fourier Transform in Embedded GPUs (Video): Video of conference presentation

vNV-Heap: An Ownership-Based Virtually Non-Volatile Heap for Embedded Systems
Markus Elias Gerber, Luis Gerhorst, Ishwar Mudraje, Kai Vogelgesang, Thorsten Herfet, and Peter Wägemann
(Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany; Saarland University, Germany)

Info

Results Reproduced Article: pldiws25lctesmain-p94-p (type: Full Paper) doi:10.1145/3735452.3735534

vNV-Heap: An Ownership-Based Virtually Non-Volatile Heap for Embedded Systems (Video): Video of conference presentation

Implementation and Evaluation for "vNV-Heap: An Ownership-based Virtually Non-Volatile Heap for Embedded Systems" (doi:10.1145/3712433): This artifact contains the implementation and evaluation for the paper "vNV-Heap: An Ownership-based Virtually Non-Volatile Heap for Embedded Systems". The evalutation part consists of all benchmarks and scripts required to measure the implementation and create plots from the measured data.

Compiler Technology and Auto-tuning

JetCert: A Self-Adaptive Compilation Framework for Fast and Safe Code Execution
Arman Cham Heidari and Mehran Alidoost Nia
(Shahid Beheshti University, Iran)

Info

Artifacts Functional

Results Reproduced Article: pldiws25lctesmain-p64-p (type: Full Paper) doi:10.1145/3735452.3735528

JetCert: A Self-Adaptive Compilation Framework for Fast and Safe Code Execution (Video): Video of conference presentation

JetCert: A Self-Adaptive Compilation Framework for Fast and Safe Code Execution (Artifact) (doi:10.5281/zenodo.15378813): JetCert is a Docker-packaged, self-adaptive compilation framework whose control logic follows the classic Monitor-Analyse-Plan-Execute (MAPE) loop. When you start the container (docker run --name jetcert_container -it armanheids/jetcert), the framework parses each application module (e.g., cryptography, physics, ...

Grouptuner: Efficient Group-Aware Compiler Auto-tuning
Bingyu Gao, Mengyu Yao, Ziming Wang, Dong Liu, Ding Li, Xiangqun Chen, and Yao Guo
(Peking University, China; ZTE Corporation, China)

Results Reproduced Article: pldiws25lctesmain-p68-p (type: Full Paper) doi:10.1145/3735452.3735530

Grouptuner: Efficient Group-Aware Compiler Auto-tuning (Video): Video of conference presentation

Artifact for GroupTuner: Efficient Group-Aware Compiler Auto-Tuning at LCTES'25 (doi:10.5281/zenodo.15348539): The artifacts in this paper are in the form of standalone Python scripts for the experiments. Our experiments are primarily tested on GCC 9.2.0, and different compiler versions and hardware may cause the results to vary. Due to the potential for performance variability across different environments, particularly in VM ...

Multi-level Machine Learning-Guided Autotuning for Efficient Code Generation on a Deep Learning Accelerator
JooHyoung Cha, Munyoung Lee, Jinse Kwon, Jemin Lee, and Yongin Kwon
(UST, Republic of Korea; ETRI, Republic of Korea)

Publisher's Version Article: pldiws25lctesmain-p167-p (type: Full Paper) doi:10.1145/3735452.3735538

Multi-level Machine Learning-Guided Autotuning for Efficient Code Generation on a Deep Learning Accelerator (Video): Video of conference presentation

DSP-MLIR: A Domain-Specific Language and MLIR Dialect for Digital Signal Processing
Abhinav Kumar, Atharva Khedkar, Hwisoo So, Megan Kuo, Ameya Gurjar, Partha Biswas, and Aviral Shrivastava
(Arizona State University, USA; Yonsei University, Republic of Korea; MathWorks, USA)

Results Reproduced Article: pldiws25lctesmain-p60-p (type: Full Paper) doi:10.1145/3735452.3735527

Reproduction Package (Docker container) for DSP-MLIR: A Domain-Specific Language and MLIR Dialect for Digital Signal Processing (doi:10.5281/zenodo.15549101): This is the artifact accompanying our research on DSP-MLIR, a domain-specific compiler framework for digital signal processing applications. The artifact was submitted for evaluation as part of our paper and includes the infrastructure necessary to reproduce all key results. For ease of use and reproducibility, we ...

Systems

R-Visor: An Extensible Dynamic Binary Instrumentation and Analysis Framework for Open Instruction Set Architectures
Edwin Kayang, Mishel Jyothis Paul, Eric Jahns, Muslum Ozgur Ozmen, Milan Stojkov, Kevin Rudd, and Michel A. Kinsy
(Arizona State University, USA; University of Novi Sad, Serbia)