ASYDE 2026 – Preliminary Table of Contents

8th International Workshop on Automated and verifiable Software sYstem DEvelopment (ASYDE 2026)

Frontmatter

Papers

Constrained Automated Requirements Formalization for Rigorous Analysis with Alloy
Viktoria Koscinski and Mehdi Tarrit Mirakhorli
(Colorado State University, USA; University of Hawaii at Manoa, USA)

Article Search Article: asews26asydemain-id4-p (type: Full Paper (8 pages)) doi:10.1145/3843777.3844526

Controller Mimicking for On-the-Fly DES Reachability Control
Florencia Zanollo, Fuyuki Ishikawa, Sebastian Uchitel, and Víctor A. Braberman
(University of Buenos Aires, Argentina; CONICET, Argentina; National Institute of Informatics, Japan; Imperial College London, UK; Universidad de San Andres, Argentina)

Article Search Article: asews26asydemain-id6-p (type: Full Paper (8 pages)) doi:10.1145/3843777.3844527

From Statistical Code Generation to Correct-by-Construction AI Programming: A Basis-Function Composition Framework
Yu Wu and Yuchen Yang
(Chengdu University of Technology, China; TU Munich, Germany)

Article Search Article: asews26asydemain-id8-p (type: Full Paper (8 pages)) doi:10.1145/3843777.3844528

WanderVision: Scenario-Based GUI Testing for Smart TVs via Vision-Language Models
Sihyun Ahn, Juyeon Yoon, Taehyoung Kim, Eunki Song, and Shin Yoo
(Korea Advanced Institute of Science and Technology, Republic of Korea; LG Electronics, Republic of Korea)

Article Search Article: asews26asydemain-id10-p (type: Full Paper (8 pages)) doi:10.1145/3843777.3844529

Towards a Vertically Integrated Compiler Infrastructure to Improve Solver Time during Symbolic Execution
Sören Tempel and Christian Dietrich
(Technische Universität Braunschweig, Germany)

Article Search Artifacts Available Article: asews26asydemain-id11-p (type: Full Paper (8 pages)) doi:10.1145/3843777.3844530

Artifacts for ASYDE'26: Towards a Vertically Integrated Compiler Infrastructure to Improve Solver Time during Symbolic Execution (doi:10.5281/zenodo.22095861): This dataset contains the files required to reproduce the evaluation results of the ASYDE'26 paper: Towards a Vertically Integrated Compiler Infrastructure to Improve Solver Time during Symbolic Execution. Specifically, it includes the files necessary to reproduce Figure 5 and 6 as well as Table 1 of the manuscript.

STAFF: Towards Translating Formal Verification Benchmarks between Formal Specification Languages
Merlijn Sevenhuijsen
(TRATON, Sweden; KTH Royal Institute of Technology, Sweden)

Article Search Article: asews26asydemain-id14-p (type: Full Paper (8 pages)) doi:10.1145/3843777.3844531

Systematic Evaluation of Security Flaws in Low-Level Code Generated by LLMs
Fynn Janson, Peter Barth, and Eric Heim
(Mannheim University of Applied Sciences, Germany)

Article Search Article: asews26asydemain-id18-p (type: Short Paper (4 pages)) doi:10.1145/3843777.3844532

Correct-by-Construction Evolution of Digital Twins for Real-Time Autonomous Systems
Luca Brodo, Giuseppe Scalora, and Stefan Henkler
(Hamm-Lippstadt University of Applied Sciences, Germany)

Article Search Article: asews26asydemain-id20-p (type: Full Paper (8 pages)) doi:10.1145/3843777.3844533

Dead-End Ratio: A Behavioral Model Quality Metric for Constraint-Aware Runtime Verification
Natalia Dybczak, Jagoda Flejmer, and Radosław Klimek
(AGH University of Krakow, Poland)

Article Search Article: asews26asydemain-id21-p (type: Full Paper (8 pages)) doi:10.1145/3843777.3844534

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